Job Description

Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Responsibilities and Description: The Physical Design and Verification Engineer will be responsible for leading the team efforts on the functional verification of neural recording and stimulation SoCs, which include low-power processors, digital signal processing, hardware accelerators, and analog/mixed-signal IPs. The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly. Required Qualifications: Bachelor of Science (B.S.) degree in computer science or a related field, or equivalent experience Minimum 3 years of experience in digital ASIC verification Excellence in SystemVerilog Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell Experience with code coverage and regression setup Preferred Qualifications: Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools Experience building test benches, testing, and debugging for a complex system-on-chip Experience in formal verification Functional modeling experience and logic verification with SystemVerilog, SystemC/C++ Experience with IEEE-1801 (UPF) based design simulation flows Experience with low power gate level simulations Exposure with low power formal verification flows Strong hands-on experience in verification methodologies such as UVM Knowledge of ARM/RISC-V processor, AMBA bus Knowledge of power aware verification Experience with FPGA/emulation Experience with lab system bring up, writing diagnostic, and lab debugging Experience with build tools such as CMake and Bazel #J-18808-Ljbffr Neuralink

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